IEN - Micro/Nano Fabrication Facility
STS ICP
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Equipment Description

The Georgia Tech STS ICP is a CMOS-compatible tool used for integrated MEMS-CMOS processes, and is meant for narrow (<10 micron in width) high aspect-ratio trench etching (DRIE) in silicon and SOI wafers. This system is used only for etching high aspect-ratio trenches in silicon (BOSCH process) and 4" SOI wafers.

Functions

  • Deep Silicon Trench Etching (Bosch)
  • SOI Wafer Etching

Substrates

  •  Si, poly-Si, a-Si

Mask

  • Resist, SiO2, Si3N4
  • No SU-8

Coil

  • ​​1000W 13.56 MHz ENI ACG-10B

Platen

  • HF: 500W 13.56 MHz ENI.
  • LF: 300W 380 kHz AEI

8-pin ceramic clamp for 100mm w/ HBC Lip Seal

Gases

  • ​​C4F8, SF6, O2, Ar

Process Pressure

  • 2 – 80 mTorr

Temperature

  • ​​5-40 C (platen), 40 C (walls), 45 C (lid)

Vendor Specifications

  • 30:1 aspect ratio 1um trench
  • 15:1 aspect ratio 1um SOI w/ minimal notching

Actual Installation Results

  • 43:1 aspect ratio 1um trench gratings

Recent Service/Modifications

  • Kalrez seals for throttle valve
  • Chamber liner laser cleaning through Pen-Tec

SiO2 mask

High gas flow rates

Higher etch to passivation step times ratios

Lower platen power

Rules

  • Silicon etching only
  • No exposed metal
  • CMOS compatible only
  • No through-wafer w/o carrier
  • Backside of wafer must be clean
Institute Georgia Tech
Department IEN - Micro/Nano Fabrication Facility
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Pettit Cleanroom
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