IEN - Micro/Nano Fabrication Facility
3.5.1 Dielectric Etching

This section contains the standard dielectric etch recipes for all GT RIE and ICP equipment: Ctrlayer RIE 2, Ctrlayer RIE 1, Oxford End-Point RIE, Unaxis 790 RIE, Plasma Therm RIE (Right Chamber), and  Plasma Therm ICP (Left Chamber).

Comparison of Oxide Etch Details for GT RIE and ICP Equipment

Comparison oxide etch

CTRLayer RIE 2

  • Location: Marcus Cleanroom
  • Etching Capabilities:
    • Silicon Dioxide
    • Descum
  • Sample size:
    • Pieces to 8” wafer
    • Up to four, 4” wafers or a single 6” wafer at one time
  • Standard Recipes:

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CTRLayer RIE 1

  • Location: Marcus Cleanroom
  • Etching Capabilities:
    • Silicon Dioxide
    • Descum
  • Sample size:
    • Pieces to 8” wafer
    • Up to four, 4” wafers or a single 6” wafer at one time
  • Standard Recipes:

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Oxford End-Point RIE

  • Location: Marcus Cleanroom
  • Etching Capabilities:
    • Silicon Dioxide
    • Descum
  • Sample size:
    • Pieces to 8” wafer
  • Standard Recipes:

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Unaxis 790 RIE

  • Location: Marcus Cleanroom
  • Etching Capabilities:
    • Silicon Dioxide
    • Descum
  • Sample size:
    • Pieces to 8” wafer
  • Standard Recipes:

Uniaxis RIE

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Plasma Therm RIE (Right Chamber)

  • Location: Petitt  Cleanroom
  • Etching Capabilities:
    • Silicon Dioxide
    • Descum
  • Sample size:
    • Pieces to 4” wafer
    • Up to four, 4” wafers at a time
  • Standard Recipes:

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Plasma Therm ICP (Left Chamber)

  • Location: Petitt  Cleanroom
  • Etching Capabilities:
    • Silicon Dioxide
    • Descum
  • Sample size:
    • Pieces to 4” wafer. Pieces has to be placed on a four inch Si wafer with cool grease, or with a kapton tape
  • Standard Recipes:

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Contact Information
The Institute for Electronics and Nanotechnology at Georgia Tech
345 Ferst Drive, Atlanta GA, 30332

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