IMS- Micro/Nano Fabrication Facility
3.5.2 Si/SOI Etching

This section contains the standard Silicon and SOI etch recipes for all GT RIE and ICP equipment: STS ICP, STS HRM ICP, Plasma Therm ICP, and Plasma Therm RIE

STS ICP

  • Location: Pettit Cleanroom
  • Etching Capabilities:
    • Silicon Etch
    • SOI
    • Silicon Blanket Etch
  • Sample size:
    • Pieces to 4” wafer. Pieces have to be placed on a four inch SiO2/Si wafer with cool grease, or with a kapton tape.
  • Standard Recipes:

STS ICP Si etch

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STS HRM ICP

  • Location: Marcus Cleanroom
  • Etching Capabilities:
    • Silicon Etch
    • Smooth Side Wall Etch for Silicon
    • Silicon Blanket Etch
  • Sample size:
    • Pieces to 4” wafer. Pieces have to be placed on a four inch SiO2/Si wafer with cool grease, or with a kapton tape.
  • Standard Recipes:

STS HRM Si etch

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Plasma Therm ICP (Right Chamber)

  • Location: Pettit Cleanroom
  • Etching Capabilities:
    • Silicon Etch
  • Sample size:
    • Pieces to 4” wafer. Pieces have to be placed on a four inch SiO2/Si wafer with cool grease, or with a kapton tape.
  • Standard Recipes:

Plasma Therm ICP Si etch


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Contact Information
The Institute for Electronics and Nanotechnology at Georgia Tech
345 Ferst Drive, Atlanta GA, 30332

For process support please click below